Generally, semiconductor devices are fabricated using a semiconductor substrate having a cell array region and a peripheral circuit region. The semiconductor substrate has a plurality of cell gate patterns in the cell array region and a plurality of peripheral gate patterns in the peripheral circuit region. The cell gate patterns and the peripheral gate patterns are simultaneously formed on the semiconductor substrate for simplifying a semiconductor manufacturing process. The cell gate patterns and the peripheral gate patterns are formed to overlap impurity diffusion regions disposed in the semiconductor substrate. Also, the cell gate patterns and the peripheral gate patterns are covered with an insulating layer, which is selected for simplifying a semiconductor manufacturing process. As a result, using the selected insulating layer results in the same heat budget imposed on the cell gate patterns and the peripheral gate patterns, and thus may provide a way for easily controlling electrical characteristics of a semiconductor device.
However, when the selected insulating layer is used, the electrical characteristics of the semiconductor device may not be easily controlled according to a reduced design rule of a semiconductor device. This is because the cell and peripheral gate patterns and impurity diffusion regions should be smaller in size as compared with prior devices to the reduced design rule for the sake of high integration density. When the selected insulating layer is used, the size of the impurity diffusion regions cannot be smaller below the cell and/or peripheral gate patterns as compared with prior to the reduced design rule. Accordingly, using the selected insulating layer may prevent a semiconductor device from having high integration density.
A semiconductor integrated circuit device having a selective insulating layer is disclosed in Japanese Laid-Open Patent Publication No. JP11-17129 to Yoshida Makoto et al. According to Japanese Laid-Open Patent Publication No. JP11-17129, a semiconductor substrate having a logic portion and a DRAM portion is prepared. Gate electrodes and semiconductor regions are formed in the logic portion and the DRAM portion of the semiconductor substrate. The semiconductor regions are formed to overlap the gate electrodes in the logic portion and the DRAM portion of the semiconductor substrate. The semiconductor regions are impurity diffusion regions. A silicon oxide layer is disposed on the semiconductor substrate to cover the gate electrodes. As a result, the silicon oxide layer constitutes the semiconductor integrated circuit device together with the gate electrodes and the semiconductor regions.
However, the semiconductor integrated circuit device cannot have a smaller size of the semiconductor regions below the gate electrodes as compared with prior to a reduced design rule while the silicon oxide layer is formed in the logic portion and the DRAM portion of the semiconductor substrate. This is because the silicon oxide layer is covered with the logic portion and the DRAM portion at the same time, and imposes the same heat budget on the semiconductor regions. Therefore, the semiconductor regions may be diffused downwardly from the gate as much as prior to the reduced design rule. As a result, the silicon oxide layer may not correspond to the reduced design rule, so that it can be difficult to realize a semiconductor integrated circuit device having high integration density.